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# Digital Logics

### Examination 2018

#### Group B

Attempt any SIX questions. [6x5 = 30]

11.Subtract: 675.6 – 456.4 using both 10's and 9's complement.[5]

12.What is universal logic gate? Realize NAND and NOR as an universal logic gates. [1+2+2]

13. Simplify (using K- map) the given Boolean function F in both SOP and POS using don't care conditions D: B'CD' + A'BC'D F = B'C'D' + BCD' + ABCD' [2+3]

14.Define encoder: Draw logic diagram and truth table of octal - to - binary encoder. [1 + 4]

15.What is D flip-flop? Explain clocked RS flip-flop with its logic diagram and truth table.[1+4]

16.Design MOD - 5 counter with state and timing diagram.[2+1+2]

17. Design a 4 - bit serial into parallel- out shift register with timing diagram. [3+2]

#### Group C

Attempt any TWO questions.[2x10 = 20]

18. Write difference between PLA and PAL. Design a PLA circuit with given functions.
F1 (A, B, C) = Σ (2, 3, 5)
F2 (A, B, C) = Σ (0, 4, 5, 7).
Design PLA program table also.[3+7]

19.Define D flip-flop. Design a Master-slave flip-flop by using JK flip-flop along with its circuit diagram and truth table. [2+8]

20.Write down the difference between asynchronous and synchronous counter. Design a 4-bit binary ripple counter along with its circuit, state and timing diagram. [3+7]

### Examination 2019

#### Group B

Attempt any Six question

2. Subtract: 1010.110 - 101.101 using both 2's and 1's complement.

3. Simplify (using k-map) the given Boolean unction in both SOP and POS using the don't case condition d:
f(A,B,C,D) = π(0,1,3,7,8,12) πd (5,10,13,14)

4. Define decoder. Draw logic diagram and truth table of 3 to 8-line decoder.

5. Define ROM. Implement the following combinational logic function using ROM:

 A1 A0 F1 F2 0 0 1 0 0 1 0 1 1 0 1 1 1 1 1 0

6. What are the drawbacks of clocked RS Flip Flop? Explain the operation of JK Flipflop along with its circuit diagram and characteristic table.

7. What is T-Flip Flop? Explain clocked JK Flip-Flop with its logic diagram and truth table.

8. Design MOD-7 counter with state and timing diagram

#### Group C

Attempt any Two question

9. Define PLA. Design PLA circuit with given funtion.
F1(A,B,C) = Σ (3,5,6,7)
F2(A,B,C) = Σ (0,2,4,7).
Design PLA Program table also

10. Distinguish between sequential and combinational logic with example? Discuss the design procedure of combinational logic.

11. A sequential circuit with two D flip flops, A and B, two inputs x and y, and one output z, us specified by the following next state and output equations.
A(t + 1) = x'y + xA
B(t + 1) = x/B + xA
z = B
a) Draw the logic diagram.
b) Derive the state table.
c) Derive the state diagram.

### Examination 2020

#### Group B

Attempt any SIX questions. [6x5 = 30]

2. Define Digital Logic. Explain digital signal with its applications, advantages and disadvantages. [1 + 4]

3. Define positional number System [1]
calculate following: a) Subtract 21 from 35 using 2's complement method [2]
b) Convert (62.75)10 into single precision floating point format [2]

4. Define universal gate. Explain Universal gates with their graphical symbol, algebraic expression, truth table, and Venn diagram [1 + 4]

5. Define Decoder. Explain binary to octal converter with block diagram, truth table and logic diagram[1 + 4]

6. Simplify the Boolean function F(w,x,y,z) = π(0,2,4,6,8,10,12,14) and don't care conditions d(w,x,y,z) = π(1,3,9,11) using K-Map method for both SOP and POS form [2.5 + 2.5]

7. Degine Multiplexer. Explain 4:1 multiplexer with its block diagram, truth table and logic diagram [1 + 4]

8. Write short Notes on (any Two): [2.5 + 2.5]